(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device including a floating gate and/or charge trapping type of memory device.
(b) Description of the Related Art
A flash memory device is a non-volatile memory device which maintains data stored therein as long as an erasing operation is not applied. Compared to a volatile memory device such as a DRAM, a non-volatile memory device has merits in that circuits for a refresh operation are unnecessary, and power consumption can be reduced. However, a high voltage should be applied to input or erase data in a non-volatile memory device, and an additional storage structure is used to retain data in a non-volatile memory device when power is not applied. Therefore, a non-volatile memory device may have a relatively complicated structure and manufacturing process as compared to certain types of volatile memories (e.g., static RAM, or SRAM).
Non-volatile memory devices may be classified into a floating gate type of device and a floating trap type of device. A floating trap type of device is programmed by storing charges on a charge trapping surface between a semiconductor substrate and a gate electrode. A floating trap generally comprises a charge storage (or charge trapping layer) generally formed from silicon nitride, a blocking insulation layer formed on an upper part or upper surface of the charge storage layer, and a tunneling insulation layer formed on a lower part or a lower surface of the charge storage layer. A typical structure for a floating trap type device is a SONOS (silicon oxide nitride oxide semiconductor) structure, and a SONOS structure has a floating trap which generally comprises of a nitride layer-oxide layer interface in an ONO (oxide-nitride-oxide) structure.
In forming an embedded SONOS device, such a SONOS device and a logic device should be simultaneously formed. However, part of a SONOS process may be performed before forming a well in a process for forming a logic device, because a SONOS device should have characteristics of a conventional logic device. Therefore, an ONO layer may be damaged when ion-implantation for forming a well in a logic device is performed in the presence of an exposed ONO pattern in a SONOS device region. Consequently, when an ONO layer is damaged by such ion implantation, the ONO layer may later explode or otherwise fail.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form prior art or other information that may be already known in this or any other country to a person of ordinary skill in the art.